High Performance Inter-chip Signalling

The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the performance of digital systems. In intra-system interfaces where both latency and bandwidth are important, source-synchronous parallel channels have been adopted as the most effective solution. This work investigates receiver and clocking circuit design techniques for increasing the signalling rate and robustness of such channels. One of the main problems arising in the reception of high speed signals is the adverse effects of high frequency noise. To alleviate these effects, a new class of receiver structures that utilize current integration is proposed. The integration of current on a capacitor based on the incoming signal polarity effectively averages the signal over its valid time period, therefore filtering out high frequency noise. An experimental transceiver prototype utilizing current integrating receivers was designed and fabricated in a 0.8 μm CMOS technology. The prototype achieves a signaling rate of 740 Mbps/pin operating from a 3.3V supply with a bit error rate of less than 10-14. The second major challenge of inter-chip communication is the design of clock generation and synchronization circuits. Delay locked loops are an attractive alternative to VCObased phase locked loops due to their simpler design, intrinsic stability, and absence of phase error accumulation. One of their main problems however is their limited phase capture range. A dual loop architecture that eliminates this problem is proposed. This architecture employs a core loop to generate finely spaced clock edges, which are then used by a peripheral loop to generate the output clock through phase interpolation. Due to its digital control, the dual loop can offer great flexibility in the implementation of phase acquisition algorithms. A dual DLL prototype was fabricated in a 0.8 μm CMOS technology. The prototype achieves 80KHz-400MHz operating range, 12-ps rms jitter and 0.4-ps/mV jitter supply sensitivity.